1. Field of the Invention
The present invention is related to a pixel array, and more particular to a pixel array having a relatively better display quality.
2. Description of Related Art
With the continuous advancement of the liquid crystal display device towards to the large-size display standard, the wide viewing angle techniques of the liquid crystal display panel are continuously developed in order to overcome the viewing angle problem of the large-size display device. Among the wide viewing angle techniques, the multi-domain vertical alignment (MVA) liquid crystal display panel and the polymer stabilized alignment (PSA) liquid crystal display panel are the most common wide viewing angle techniques. To improve the color washout problem of the liquid crystal display panel, the advanced-MVA liquid crystal display panel is disclosed. In the technique of the advanced-MVA liquid crystal display panel, each of the sub-pixel regions is divided into a main display region and a sub-display region. By using the adequate circuit design or the adequate driving method, the main display region and the sub-display region in the same sub-pixel region respectively have different bias voltages. Thus, the color washout problem can be overcome. In the current technique, the concept that each of the sub-pixel regions is divided into a main display region and a sub-display region is applied into the technique of the polymer stabilized alignment liquid crystal display panel.
FIG. 1 is an equivalent circuit diagram of a pixel array and FIG. 2 is a schematic view of a single sub-pixel shown in FIG. 1. As shown in FIG. 1 and FIG. 2, a pixel array 100 comprises a plurality of sub-pixels P1, and each of the sub-pixels P1 comprises a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, a first pixel electrode ITO1 electrically connected to the first thin film transistor TFT1, a second pixel electrode ITO2 electrically connected to the second thin film transistor ITO2. The first pixel electrode ITO1 is coupled to a common line COM1 to form a first storage capacitor Cs1. Further, the first pixel electrode ITO1 is coupled to a common electrode (not labeled) on the opposed substrate (such as the color filter substrate) to form a first liquid crystal capacitor CLC1. Similarly, the second pixel electrode ITO2 is coupled to a common line COM2 to form a second storage capacitor Cs2. Further, the second pixel electrode ITO2 is coupled to a common electrode (not labeled) on the opposed substrate (such as the color filter substrate) to form a second liquid crystal capacitor CLC2.
As shown in FIG. 1 and FIG. 2, in the sub-pixel P1 electrically connected to the scan line SL(n−1), the gates G1 and G2 of the first thin film transistor TFT 1 and the second thin film transistor TFT2 are electrically connected to the scan line SL(n−11) and the gate G3 of the third thin film transistor TFT3 is electrically connected to the next scan line SL(n). Moreover, the source S3 of the third thin film transistor TFT3 is electrically connected to the second pixel electrode ITO2 and the drain D3 of the third thin film transistor TFT3 is coupled to the first pixel electrode ITO1 to form a first capacitor Ccs-a. Furthermore, the drain D3 of the third thin film transistor TFT3 is coupled to the common line COM1 under the first pixel electrode ITO1 to form a second capacitor Ccs-b. When a high voltage (Vgh) is applied onto the scan line SL(n−1), the image data is written into the sub-pixel through the data lines DL(m−1) and DL(m), wherein the sub-pixel is connected to the scan line SL(n−1) . Meanwhile, the first pixel electrode ITO1 and the second pixel electrode ITO2 are at the same voltage level. Then, when a high voltage is applied onto the scan line SL(n), the first capacitor Ccs-a and the second capacitor Ccs-b lead to that the first pixel electrode ITO1 and the second pixel electrode ITO2 are at different voltage levels.
Since the drain D2 of the second thin film transistor TFT2 crosses over the first pixel electrode ITO1 so as to be connected to the second pixel electrode ITO2, a parasitic capacitance Cx1 is generated between the drain D2 of the second thin film transistor TFT2 and the first pixel electrode ITO1. Moreover, since the drain D3 of the third thin film transistor TFT3 crosses over the second pixel electrode ITO2, a parasitic capacitance Cx2 is generated between the drain D3 of the third thin film transistor TFT2 and the second pixel electrode ITO2. The parasitic capacitances Cx1 and Cx2 decrease the increasing of the voltage difference between the first pixel electrode ITO1 and the second pixel electrode ITO2. Thus, the color washout problem cannot be effectively improved. Hence, how to prevent the display quality from being affected by the parasitic capacitances Cx1 and Cx2 in the sub-pixel P1 is one of the important issues should be overcome.